FPGAs in Large-Scale Computer Systems

As modern data center workloads become increasingly complex, constrained and critical, mainstream “CPU-centric” computing can no longer keep pace. Future data centers are moving towards a more fluid model, with computation and communication no longer localized to commodity CPUs and routers. Next generation “data-centric” data centers will “compute everywhere,” whether data is stationary (in memory) or on the move (in network). Reconfigurable hardware, in the form of Field Programmable Gate Arrays (FPGAs), are transforming ordinary clouds into massive supercomputers. We will highlight many ways to deploy FPGAs in a data center node, such as traditional back-end accelerators, tightly coupled off-load processors, Smart NICs, Bump-in-the-Wire, and even in the router itself. We will also discuss our efforts to make these devices accessible globally accessible, through deeper integration into software stacks, transparent generation of custom hardware stacks, and device management using reconfigurable hardware operating systems.

Recently, we have focused on using FPGAs as a way to address practical limitations to widespread adoption of Multi Party Computation (MPC) implementations.

  • Bridging the performance gap for MPC-unsecured operations by using hardware accelerators, specifically FPGAs, to offload existing protocols. This goes beyond just implementing basic MPC circuits, and instead takes a first principles approach towards exploring how hardware (as well as the enabling infrastructure) is built, deployed, instrumented, and optimized in the context of MPC. 
  • Improving protocols used for MPC FPGAs so that communication and computation are equally bound in the implementation, and performance improves in tandem with increases in both network and compute capability. This involves: i) identifying different approaches used to implement MPC in hardware, ii) identifying the benefits and limitations of limitations of these approaches, iii) mapping protocols to application contexts where they are best suited, and iv) improving the computational performance of protocols. Work has already been done on implementing Secret Sharing (SS) as an MPC protocol, and results for experiments with SS are available.
  • Facilitating the use of MPC in real-world scenarios by abstracting the complexities such as selecting protocols, adapting these protocols based on the target application context, implementing circuits, scaling these circuits based on available technology, and integrating the FPGA into the application software flow. 

For more information on this project and the unique partnership that produced it, please see the website of the Red Hat Collaboratory at Boston University.

Additional Information on how to build an open-source toolchain for FPGAs can be found in the article by Ahmed Sanaullah in Red Hat Research Quarterly magazine Volume 1, Issue 3.

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