Investigate Cache and Memory Bandwidth Limitation Support in Xeon Processors

Xeon x86 cores have cache and memory bandwidth limitation support that is not currently available through simple interfaces in the kernel. The goal is to
make this functionality available, (maybe part of cgroups) so that KVM VMs or containers can be started with arguments stating “is guaranteed to get at least/most x% of cache/memory bandwidth”. This is useful for predictable workloads (real-time etc) and also HPC.

Tracked here in Taiga

Ulrich Drepper

Team: Office of the CTO
Location: Remote DE
Boston Metro RIG