Processor Extension to Predict Future States

This project aims to design a processor extension (probably RISC-V based) to use super-charged prediction in the CPU where it would wait. E.g., memory access, pipeline stalls. The goal is to predict future states of the machine without performing the intermediate steps.

Tracked here in Taiga

Ulrich Drepper

Team: Office of the CTO
Location: Remote DE
Boston Metro RIG