Vizualizace práce CPU

This thesis is intended to be a complement for learning about the RISC pipeline. Product of this thesis is a web application. After reviewing various tools and libraries suitable for this work, we have chosen two main libraries React and Redux. The created solution allows the instruction flow to be displayed in the RISC pipeline as well as states of the registers and the memory. It makes easy to perform transitions between the various parts of the visualization. This visualization allows a basic understanding of the RISC pipeline principles and also individual assembly instructions.

University

Faculty of Information Technology

Date of Completion

2016

Resources

Leader

Vojnar Tomáš

Consultant

Tišnovský Pavel

Student

Ďurčo Marián