Jose Renau is a professor at the CSE department from the UC Santa Cruz. His area of research is computer architecture, focusing on productive hardware design flows (Live Hardware Design Flow or LiveHD, architectural simulators like ESESC, new hardware description languages like Pyrope, and new design methodologies like Fluid Pipelines), out-of-order cores, and RISC-V verification. Past projects include Thread Level Speculation, infrared thermal measurements and power modeling, and design effort metrics/models. Prof. Renau has a PhD in Computer Science from the University of Illinois at Urbana-Champaign. He is the current IEEE TCMM Chair.

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