RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

February 28, 2023

Today edge devices commonly connect to the cloud to use its storage and compute capabilities. This leads to security and privacy concerns about user data. Homomorphic Encryption
(HE) is a promising solution to address the data privacy problem as it allows arbitrarily complex computations on encrypted data without ever needing to decrypt it. While there has been a lot of work on accelerating HE computations in the cloud, little attention has been paid to the message-to-ciphertext and ciphertext-to-message conversion operations on the edge. In this work, we profile the edge-side conversion operations, and our analysis shows that during conversion error sampling, encryption, and decryption operations are the bottlenecks. To overcome these bottlenecks, we present RISE, an area and energy-efficient RISCV SoC. RISE leverages an efficient and lightweight pseudorandom number generator core and combines it with fast sampling techniques to accelerate the error sampling operations. To accelerate the encryption and decryption operations, RISE uses scalable, data-level parallelism to implement the number theoretic transform operation, the main bottleneck within the
encryption and decryption operations. In addition, RISE saves area by implementing a unified en/decryption datapath, and efficiently exploits techniques like memory reuse and data reordering to utilize a minimal amount of on-chip memory. We evaluate RISE using a complete RTL design containing a RISC-V processor interfaced with our accelerator. Our analysis reveals that for message-to-ciphertext conversion and ciphertextto-message conversion, using RISE leads up to 6191.19× and 2481.44× more energy-efficient solution, respectively, than when using just the RISC-V processor.

Zahra Azad, Guowei Yang, Rashmi Agrawal, Student Member, IEEE, Daniel Petrisko, Student Member, IEEE, Michael Taylor, Senior Member, IEEE, Ajay Joshi, Senior Member, IEEE

Z. Azad, G. Yang, R. Agrawal, D. Petrisko, M. Taylor and A. Joshi, “RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2023.
Read the paper