RISC-V is an increasingly prevalent hardware architecture in embedded systems, and it’s beginning to serve as the base architecture for many new AI accelerators. It is an instruction set architecture (ISA) with roots similar to Arm and other RISC-based architectures, but with a key difference: RISC-V is developed by a community-based standards organization, RISC-V International, that fosters a collaborative ecosystem of hundreds of companies and individuals. Companies like Tenstorrent, SiFive, and Rivos (now Meta) have been shifting to RISC-V because of its open, modular nature.

To highlight the capabilities of RISC-V for complex AI workloads, in February 2026 Red Hat hosted a Fedora community workshop in the Boston office, with attendees from MIT and other local universities and private companies. The workshop was held as part of World RISC-V Days in conjunction with DeepComputing, a group of RISC-V pioneers driving the growth of the RISC-V ecosystem through the development of RISC-V-based devices. DeepComputing provided most of the hardware used. Red Hatter Matt St. Onge developed the workshop to teach RISC-V fundamentals and demonstrate an AI workload, giving participants a hands-on experience with RISC-V hardware running Fedora. Jonathan Sturges helped present. Yuning Liang from DeepComputing (deepcomputing.io) brought some wonderful pre-production tidbits for show and tell, and Red Hat Engineering manager Gary Case presented on the current state of Fedora, CentOS, and RHEL support for RISC-V. 

DeepComputing presented the ROMA RISC-V PC Mainboard II (ROMA2 AI), a modular mainboard tailored for AI developers and edge computing. ROMA2 AI hosts a Neural Processing Unit (NPU) and is housed in Framework 13 laptops. The workshop focused on bringing up Fedora on the ROMA2 AI, from installing a freshly imaged NVMe SSD to walking through the booting process, cloning the workshop repository, performing a build, and running the result using the ROMA2 AI’s onboard NPU. The open nature of the RISC-V instruction set architecture is proving to be ideally suited for AI applications and accelerators. The demonstration used Ollama tools and the Deepseek7 LLM to create a server-based model interaction in natural language, showcasing the ability to get up and running quickly with three different AI hands-on exercises on RISC-V: one via webpage chatbot and the other two showcasing command-line and API interactions. 

DeepComputing also also showed two very new products, both based on the SpacemiT K3: a small System on Module (SOM) designed for robotics and a 1U-rackable server unit hosting 10 individual K3 systems and up to 512GB RAM. Red Hat engineer Charles Mirable was able to characterize the SOM during the workshop, building the Linux kernel in about 40 minutes and showing the vast increase in performance with emerging processors based on the RVA23 specification, fast becoming a de facto standard high-impact features like ratified vector processing (RVV 1.0) and virtualization.

Possibly the most interesting outcomes of the workshop were discussions and questions from the eclectic group of attendees and hosts. Topics ranged from RISC-V and the future of hardware design to the increasing reliance on AI, necessity for neural processing, and the role of global politics for hardware availability—particularly critical for RISC-V given its position as a globally developed collaborative standard. The emergence of the RVA23 version of the specification is game-changing for all RISC-V silicon manufacturers, including DeepComputing. Yuning also spoke eloquently on the need for open source software support and optimization in the RISC-V ecosystem, which is the focus of the RISE Project. The need for tightly coupled development is also the essence of hardware-software codesign, and the open RISC-V ISA enables a level of co-optimization impossible with proprietary architectures.

Given the increasing adoption of RISC-V in AI, this workshop was very timely. Visit the demo and workshop repo for yourself on GitHub, and if you’d like to attend a future workshop, or you have an interest in AI and/or RISC-V, please reach out: jefro@redhat.com.