A Plan for Practical Programming of FPGAs in the Data Center
This event in the Red Hat Research Days monthly series will take place on April 22nd from 11AM to 12:30PM EDT (5:00PM CEST, 6:00PM IDT). In this session, Martin Herbordt, professor of Electrical & Computer Engineering at Boston University, and Robert Munafo, third-year PhD student in the CAAD Lab, will report on an ongoing project that aims to use machine learning to improve the performance of programming methods for FPGAs. Ahmed Sanaullah, Red Hat senior data scientist, will lead a live discussion open to all attendees addressing varied interests in data center and FPGA development.
To leverage the flexibility and performance potential of FPGAs in the data center requires either expensive specialized engineering talent, or commercial proprietary C-to-hardware tools that yield demonstrably poor performance. This is the performance portability programmability problem (P^4).
In previous work, we found that there exists within current compilers the capability of delivering excellent FPGA performance for arbitrary C code, but that this capability is brittle, inconsistent, and requires some expertise on the part of the user to extract. Still, this result demonstrates that P^4 can be reduced to the problem of generating the correct sequence of optimizations for a particular input code and target architecture. Our hypothesis is that a solution to P^4 can be built using existing open source tools, primarily based on GCC, coupled with well-known machine learning techniques.
In this talk, we describe our plan in detail, together with problems to be solved, and outline our work to date. In particular, we report on an ongoing project that aims to use machine learning to control a newly customizable version of the GCC C compiler to automatically determine optimization pass ordering for FPGA targets specifically, and thereby improve performance as compared to existing (all proprietary) C-to-FPGA methods.
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