Why is open hardware important? How is the new RISC-V architecture bringing open hardware research to the forefront? How will this impact you? Read on to find out.
The demand for computational power continues to grow year over year, following the requirements imposed by the ever increasing number of applications and the need to process even larger amounts of data. At the same time, the approaching end of Moore’s Law and Dennard scaling means that building the same types of central processing units (CPUs) with more dense structures (i.e., a greater number of transistors) on reduced node size (i.e., a smaller physical footprint) leads to diminishing performance gains, increased energy consumption, and, consequently, more stringent cooling requirements. We can no longer expect the traditional instruction set architectures (ISA) to keep pace with ever growing demand. The future of computing needs to be more heterogeneous in nature and, just like software today, it needs to become more open.
Red Hat is closely tracking and evaluating the potential impact of the forthcoming changes on traditional computing. We are focusing our attention on several key hardware categories and subsystems (https://research.redhat.com/wp-content/uploads/2019/12/RRQ-Vol2-1.pdf).
While computer designs are becoming more heterogeneous and the importance of CPUs has diminished, CPUs will be around for a long time, especially for popular architectures like x86. An apparent lack of ISA flexibility for CPU designs, combined with ongoing academic research around creating a royalty-free instruction set, presents a unique opportunity for an open and customizable ISA to emerge. RISC-V architecture takes that challenge head on.
A brief history of RISC-V
RISC-V is a free and open ISA that hardware designers can modify and experiment with. The unique aspect of RISC-V is that its design process and the specifications are truly open. The design reflects the community’s decisions based on collective experience and research. Although the ISA is free, the processor implementation need not be: vendors can create commercial products without disclosing the underlying processor design. This is similar to the open source model for software, in that derivative work and modifications are allowed. Additionally, for any new design to use the RISC-V name or trademark, it has to maintain compatibility with the ISA.
While other architectures may claim to be open now, none of them were thought of as such at the onset…
While other architectures may claim to be open now, none of them were thought of as such at the onset or had an active ecosystem to support it going forward. This is similar to how Linux® was open for development and contributions from the start, versus SystemV or BSD, which released their source code to the community years after they had been around.
The RISC-V instruction set was developed by Professor Krste Asanović and graduate students Yunsup Lee and Andrew Waterman in May 2010, as part of the Parallel Computing Laboratory at the University of California, Berkeley. In 2015, the RISC-V Foundation (riscv.org), a nonprofit corporation controlled by its members, was founded to build an open, collaborative community of software and hardware innovators based on the instruction set. In November 2018, the RISC-V Foundation announced a joint collaboration with the Linux Foundation (linuxfoundation.org)that provides operational, technical, and strategic support. Red Hat is a Silver member of both foundations.
In the last five years the adoption of RISC-V technology has been progressively growing on a global scale, predominantly due to the following factors:
- Geo-political reach: The openness of the RISC-V design makes it more likely to be trusted across the globe. The EU, China, and India all have ongoing projects that are supporting development and adoption of RISC-V processors.
- Technical adaptability: The flexibility to modify the ISA at the register and memory level—for example, adding machine learning or database-specific instructions—provides room for better code optimization. The net-new, clean-sheet design eliminates the requirements for supporting legacy instructions and backward compatibility while increasing flexibility and lowering the design complexity.
- Accessibility: The ability to prototype and extend designs based on RISC-V ISA as a learning tool leads to large-scale adoption in academia. This means that electrical engineers entering the workforce will have the skillset to build products based on the RISC-V ISA and will in turn promote the use of RISC-V.
- Cost: Unlike any other generally available ISA RISC-V’s free-to-license model drives overall costs down, making it attractive to enterprises.
Current and future applications
Red Hat is encouraging the development of RISC-V in open source.
The areas of application for this technology range from embedded microcontrollers to general-purpose and high performance servers. The potential is great, and RISC-V cores are already being used in embedded systems and IoT devices. In the next couple of years RISC-V will likely begin to move up into the server market.
Examples of RISC-V adoption range from announcements of support in the near future from Alibaba and European Processor Initiative (european-processor-initiative.eu/accelerator) to finished products from Western Digital, NVIDIA, SiFive, and Espressif.
- Western Digital has developed SweRV, a RISC-V processor for the controller that is part of the physical disk drive—a classic high-volume, low-cost embedded application. Western Digital’s goal is to use RISC-V as the standard engine across their entire product line.
- NVIDIA is shipping millions of graphics processing units (GPUs) with an embedded RISC-V control processor that handles small but highly optimized tasks.
- SiFive currently offers two board-level products: HiFive Unleashed and HiFive1. SiFive products include two design tools, Core Designer and Chip Designer, as well as a set of RISC-V IP cores that are customized by the design tools.
- Espressif developed two SoCs, the ESP8266 and ESP32, that are extremely successful due to their low cost and many features. The most recent design, ESP32-S2, uses a RISC-V core as its ultra-low-power core.
The rate of RISC-V ISA adoption, as well as development of the RISC-V ecosystem overall, has benefited from the previous work done for other architectures using open source. For example, there is already a working and up-to-date OS and toolchain, which will only improve as the ecosystem focuses on optimizing them. That allowed RISC-V to skip traditional phases of software development and significantly lowered the barrier to entry to anyone interested in designing and using RISC-V softcores on FPGAs, or even designing their own chips. While foundry costs are still significant and building a usable system around the ISA is still non-trivial, RISC-V is free and open for use by anyone, in all types of implementations, and remains unencumbered by licensing restrictions.
Similar to the early days of any new hardware architecture enablement, there is investigative work on RISC-V going on at Red Hat. It is currently an alternative architecture in Fedora, which boots and runs on several RISC-V emulators and boards. A team of community contributors is currently working on building the latest Fedora packages for RISC-V.
While RISC-V offers the ability to innovate freely and add unique capabilities in the form of ISA extensions, it is also intended to be a fixed ISA that adheres to industry standards and embraces standardization at the hardware level. These are both critical success factors for building an effective product and software ecosystem. In the future, customers might find RISC-V-based solutions attractive, since they would be highly customizable while supporting the standards-based software that makes up Red Hat’s ecosystem.
Red Hat is encouraging the development of RISC-V in open source. We believe that open source hardware will naturally foster an ecosystem of open source software, and an open CPU architecture is a cornerstone of an open hardware platform.