Ulrich Drepper joined Red Hat again in 2017, after a seven year hiatus when he worked for Goldmann Sachs. He is part of the office of the CTO and concentrates on developing new technologies for high-performance computing (and machine learning specifically), mostly in collaboration with university groups. In his last position at Goldman Sachs he focused on the development of models and various types of stochastic algorithms to aid in operation of the technology for the entire firm. He also taught internally various classes around machine learning and other computing topics. Additionally, Ulrich was internally a consultant for all aspects related to performance, low latency, and C/C++ compilers.
His previous stint at Red Hat lasted 14 years. The last position was as member of the office of the CTO to collect and disseminate information relevant to the Red Hat Enterprise Linux product, predominently in the high-performs area. His main interests are in the areas of low-level technologies like machine and processor architectures, programming language, compilers, high-performance and low-latency computing. In addition he is interested in using statistics and machine learning for performance analysis of programs and security of application and OS environments.
- An Optimizing Operating System: Accelerating Execution With Speculation
- Kernel Techniques to Optimize Memory Bandwidth with Predictable Latency
- Unikernel Linux
- Near-Data Data Transformation
- DISL: A Dynamic Infrastructure Services Layer for Reconfigurable Hardware
- Tuning the Linux kernel
- Practical Programming of FPGAs with Open Source Tools
- Relational Memory Controller
- CoDes : A co-design research lab to advance specialized hardware projects
- Unikernels: The Next Stage of Linux’s Dominance
- E-WarP: A System-wide Framework for Memory Bandwidth Profiling and Management
- Relational Memory: Native In-Memory Accesses on Rows and Columns
- Reinforcement Learning Strategies for Compiler Optimization in High level Synthesis
- Enabling VirtIO Driver Support on FPGAs