CoDes : A co-design research lab to advance specialized hardware projects
General purpose hardware, operating systems, and application frameworks allow for fast and inexpensive development and deployment of problem-solving problems. This is all well if there are no outside pressures on performance and/or energy consumption. Then the “general” aspect of the technologies is a problem.
Specialized hardware has enabled us to fundamentally change the way we compute, communicate and store data. It allows focus on what is needed:
- Enabling more work within the same energy and hardware budget, e.g. by using specialized hardware based PCIe cards as offload accelerators
- Enabling the same work with a reduced energy and hardware budget, e.g. by running programs on low power embedded processors that have been tailored to the workload
The drawback with tapping into this new computing paradigm is that developer effort increases. Current software development cycles are based around platform-agnostic software running on top of a general purpose OS, which in turn runs on top of a general purpose computer. This lends to a heavily streamlined process that rapidly advances the software ecosystem.
With existing techniques to develop and deploy specialized hardware, developers may need to significantly change their code for every combination of underlying hardware, target workload, system stack, and overhead budget (runtime, energy usage etc). As a result, the development cycle is disrupted and can result in large timeframes for creating and maintaining code. This is a highly impractical approach for a majority of use cases.
One possible solution to the above limitation is co-design. Co-design allows us to create a development cycle that is similar in efficiency to that of software development. It focuses on building specialized hardware blocks and frameworks which have the capabilities and interfaces needed for software integration. Simultaneously, it also focuses on developing software that is also designed to improve workload efficiency, e.g. Unikernels, and contains appropriate out of the box mechanisms for taking advantage of available specialized hardware.
What is CoDes?
CoDes research lab provides the infrastructure and engineering foundation needed to support co-design based specialized hardware research. The lab is currently located at Boston University, as part of the Red Hat – Boston University collaboratory. At its core, CoDes targets:
- Automation: Replacing developer expertise requirements with Machine Learning, and automating tasks to improve productivity.
- Scalability: Across the cloud-edge continuum, having a common development ecosystem; this in particular includes hardware blocks that can be scaled based on user and system constraints.
- Tunability/Configurability: Enabling developers to configure both hardware and software to better match their requirements.
- Features: Focusing not only on features that are critical for specialized hardware workloads, but also features that can significantly boost productivity and enable exploration into innovative methods for how specialized hardware can be used.
- Portability: Move as much functionality out of the chip/board specific blocks as possible, and minimize the role of components in board support packages.
- Uniformity: Having uniform abstractions between different parts of the ecosystem. This includes both uniformity of interfaces between hardware components, as well as uniformity between devices so that specialized hardware can be leveraged by existing software stacks as much as possible.
What forms of specialized hardware will CoDes target?
Our initial focus is primarily FPGAs and microcontrollers because of the importance of these devices in modern compute environments. As shown by the illustration below, the flexibility and versatility of FPGAs enables them to play various critical roles aimed at improving the performance, power efficiency, resource utilization, security and costs for infrastructures across the cloud-edge continuum. When coupled with microcontrollers, we can add even more capability to the FPGA enhanced systems such as device management, wireless communication, remote debugging etc.
In the long run, the goal of CoDes is to target multiple forms of specialized hardware – from other forms of Dataplane Processing Units to Graphics Processing Units to even Quantum computing. This is because we have a: i) large specialized hardware pool, each with its own advantages, and ii) a large workload pool, where each workload can have its own unique combination of hardware, connectivity and code mapping strategy. As a result, there are research opportunities in exploring novel combinations of hardware+workloads that can deliver even better results than established approaches.
Why is CoDes an on-premise infrastructure?
While specialized hardware is readily available in both production and research environments, users are restricted in how they can use specialized hardware since the infrastructure is shared. These constraints limit the type of specialized hardware research that can be done.
Simply put, there is a deadlock – the current support for specialized hardware is not advanced enough to support systems research, and there is not sufficient systems research possible to advance available support for specialized hardware to address restrictions. CoDes aims to break this deadlock by adding an on-premise incubation step to the process.
CoDes is not an alternative to large infrastructures in the cloud and edge. Rather, CoDes substantially widens the pool of specialized hardware research projects by minimizing the risk of this research, and by providing researchers with more control over the software and hardware stacks. Once projects reach a certain level of completeness and reliability, they can be transitioned into larger infrastructures and the research can continue in the shared environment.
Who will be using CoDes?
There are two dimensions of collaboration that CoDes enables. CoDes brings together:
- researchers and engineers in order to ensure that a project’s scientific advancements are built on top of a strong, standard and practical engineering foundation. By leveraging the tried and tested principles of software development, we aim to progress hardware ecosystems at the same rapid pace as software ecosystems.
- researchers from various disciplines by having completed project milestones available for use by collaborators within the CoDes ecosystem. This centralization and availability of project data, coupled with the above engineering foundation, can reduce the overhead of research, validate completed efforts, help identify areas of further improvement/innovation, lower the bar for entry in specialized hardware research, and open up new exciting avenues of research.
- Practical Programming of FPGAs with Open Source Tools
- DISL: A Dynamic Infrastructure Services Layer for Reconfigurable Hardware
- Relational Memory Controller
- Near-Data Data Transformation
- Open-Source Toolchain Optimization for FPGA CAD
- RISC-V for FPGAs: benefits and opportunities
- Red Hat Research Quarterly Volume 1:3, page 10: Roll Your Own Processor: Building An Open Source Toolchain For An FPGA
- Towards Hardware as a Reconfigurable, Elastic, and Specialized Service
- Reinforcement Learning Strategies for Compiler Optimization in High level Synthesis
- Enabling VirtIO Driver Support on FPGAs
- The Future of FPGA Acceleration in Datacenters and the Cloud
- Survey and Future Trends for FPGA Cloud Architectures