Red Hat Research Quarterly

Research demo shows hardware-software co-design in action

Red Hat Research Quarterly

Research demo shows hardware-software co-design in action

The Dynamic Infrastructure Services Layer (DISL) puts the benefits of programmable hardware within reach.

Red Hat Research engineers and edge computing specialists Ahmed Sanaullah and Jason Schlessman demonstrated the potential of the Dynamic Infrastructure Services Layer (DISL) at the October 2023 Red Hat Research Day. The presentation, CoDesign in Action: Dynamic Infrastructure Services Layer (DISL), introduced an open source abstraction layer that streamlines customization of the hardware stack to meet specific application needs. The project comes from the CoDes research lab located at the Red Hat Collaboratory at Boston University.

A developer-friendly solution

The pressure on developers to optimize applications for speed, performance, and efficiency keeps growing. Programmable hardware such as Field Programmable Gate Arrays (FPGAs) offers those improvements, but proprietary tooling and inefficient development workflows have made them inaccessible to developers without specialized expertise. 

DISL, a collaborative effort between engineers and researchers at Red Hat and BU, solves that problem with an interface that allows the entire hardware stack to be fully expressed and customized using only configuration files. It also provides a library of tools for managing deployments in both wired and wireless configurations. Developers can now take advantage of the benefits of specialized hardware in a way that is portable and can be dynamically updated wirelessly as needs change.

Ben Cushing, Chief Architect, Health & Life Sciences, Red Hat, led the Research Day conversation with Ahmed and Jason as they walked the audience through the DISL project. The team demoed building a custom wireless security system using off-the-shelf components to illustrate how DISL supports quick builds of far-edge systems.

Those who missed the live Research Day event can find the recording and slides on the event page, as well as a 38-minute demo version without discussion.  In both recordings, the team discusses the value of far-edge research and FPGAs, the difficulties of using FPGAs, and the details of the DISL design before launching the demo.

To get involved

Researchers are actively seeking ideas for potential use cases.  Contact Ahmed Sanaullah and Jason Schlessman to share your thoughts.

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